Circuit and system design for neuromorphic computing and hardware, on-chip integrated voltage converters and regulators, high-speed and low-power on-chip communication circuits.
Jae-sun Seo received the B.S. degree from Seoul National University in 2001, and the M.S. and Ph.D. degree from the University of Michigan in 2006 and 2010, respectively, all in electrical engineering. He spent graduate research internships at Intel circuit research lab in 2006 and Sun Microsystems VLSI research group in 2008. From January 2010 to December 2013, he has been with IBM T. J. Watson Research Center, where he worked on energy-efficient integrated circuits for high-performance processors and cognitive computing chips. In January 2014, he joined ASU as an assistant professor in the ECEE department. Mr. Seo was a recipient of Samsung Scholarship from 2004 to 2009, received a IBM outstanding technical achievement award in 2012, and serves on the technical program committee for ISLPED.
Ph.D., electrical engineering, University of Michigan, 2010
M.S., electrical engineering, University of Michigan, 2006
B.S., electrical engineering, Seoul National University, 2001
Recognition and awards
IBM Major Outstanding Technical Achievement Award, 2012
IBM Invention Achievement Award, 2011
Samsung Scholarship Foundation Fellow, 2004-2009
Y. Liu, P. Hsieh, S. Kim, J. Seo, R. Montoye, L. Chang, J. Tierno, and D. Friedman, “A 0.1pJ/b 5-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45-nm CMOS SOI,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 400-401, February 2013.
B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishnan, L. Chang, D. Friedman, and M. Ritter, “Specifications of Nanoscale Devices & Circuits for Neuromorphic Computational Systems,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 246-253, January 2013.
J. Seo, D. Blaauw, and D. Sylvester, “Crosstalk-Aware PWM-Based On-Chip Links with Self-Calibration in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), September 2011, vol. 46, no. 9, pp. 2041-2052, September 2011.
J. Seo, B. Brezzo, Y. Liu, B. Parker, S. Esser, R. Montoye, B. Rajendran, J. Tierno, L. Chang, D. Modha, and D. Friedman, “A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons,” IEEE Custom Integrated Circuit Conference (CICC), September 2011.
J. Seo, R. Ho, J. Lexau, M. Dayringer, D. Sylvester, and D. Blaauw, “High-Bandwidth and Low-Energy On-Chip Signaling with Adaptive Pre-Emphasis in 90nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 182-183, February 2010.