Lawrence Clark

Clark_LawrenceWEBProfessor
ASU Directory Profile

GWC 234
480-727-0295
lawrence.clark@asu.edu

Research expertise
Circuits and architectures for low power and high performance VLSI, radiation hardened circuit design and CAD for VLSI

Lawrence T. Clark worked at Intel Corporation after receiving his B.S. in computer science in 1983. While completing his Ph.D. he worked at VLSI Technology Inc. designing PC chipsets. He received his Ph.D. in 1992 after receiving his M.S. in 1987, both in electrical engineering from Arizona State University. He re-joined Intel in 1992. He joined ASU in August 2004. Clark has been awarded over 70 patents, with approximately 20 pending. He has published over 100 peer-reviewed technical papers. He has approximately 15 years of industry experience in various aspects of chipset, CMOS imager, microprocessor design, test engineering, and TCAD. Clark contributed to the Pentium, Itanium, and XScale microprocessor designs. Most recently, he was a principal engineer and circuit design manager for the Intel XScale microprocessor designs. Clark has been with SuVolta Inc. in various capacities since 2009.

Collaborations and industry affiliations
Allee,DavidRay * , Clark,LawrenceT , . Neutron Detector. UNIV OF TEXAS-DALLAS (6/7/2010 – 12/31/2012).
Clark,LawrenceT * . Development of the Highly Efficient Rad-hard-by-design Microprocessor for Enabling Spacecraft (HERMES). JPL (3/10/2010 – 2/27/2011).
Vermeire,Bert * Clark,LawrenceT . Design of a hardened SDRAM integrated Circuit. SPACE MICRO, INC (7/1/2009 – 6/30/2010).
Clark,LawrenceT * Allee,DavidRay . Support Micro-RDC on the Advanced IC Design Techniques for the Prevention of Reverse Engineering of the Programmed Functionality in FPGAs. Micro-RDC (1/7/2008 – 9/14/2009).
Clark,LawrenceT * Barnaby,HughJames Holbert,KeithEdwin . High Performance, Low Power Radiation Hardened by Design Microprocessor Techniques. DOD-AFRL (8/14/2007 – 12/28/2012).
Clark,LawrenceT * . Ultra-Fast Level 2 Cache SRAM for High-Performance Military and Spaceborne Computing. Micro-RDC (3/5/2007 – 8/27/2007).

Professional preparation
Ph.D., electrical engineering, Arizona State University, 1992
M.S., electrical engineering, Arizona State University, 1987
B.S., computer science, Northern Arizona University, 1984

Recognition and awards
Senior member, IEEE
Associate editor of IEEE Transactions on Circuits and Systems II
Guest editor of J. Solid-state Circuits
Recipient of the Intel Achievement Award and multiple Intel Divisional Recognition Awards
Technical committee member for IEEE Custom Integrated Circuits Conference
Technical committee member for IEEE Nuclear and Space Radiation Effects Conference
Technical committee member for the International Symposium on Low Power Electronics and Design

Professional associations
Senior member of IEEE

Selected publication
S. K. Maurya and L. Clark, “A dynamic longest prefix matching content addressable memory for IP routing,” IEEE Trans. on VLSI Systems, vol. 19, no. 6, pp. 963-972, June 2011.

L. Clark, D. Patterson, N. Hindman, K. Holbert, S. Maurya, and S. Guertin, “A Dual Mode Redundant Approach for Microprocessor Soft Error Hardness,” IEEE Trans. Nuc. Science, vol. 58, no. 6, pp. 3018-3025, Dec. 2011.

G. Sampson and L. Clark, “Low power race free programmable logic arrays,” IEEE J. Solid State Circuits, vol. 44, no. 3, pp. 935-946, Mar. 2009.

D. Allee, E. Bawolek, L. Clark, J. Fernando, Z. Li, K. Kaftanoglu, S. O’Rourke, H. Shivalingaiah, R. Shringarpure, S. Uppili, S. Venugopal, and B. Vogt, “Degradation effects in a-Si:H thin film transistors and their impact on circuit performance,” IEEE Trans. Elec. Dev., vol. 56, no. 6, pp. 1166-1176, June 2009.

G. Samson, N. Ananthapadmanabhan, S. Badrudduza, and L. Clark, “Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories,” IEEE J. Solid State Circuits, vol. 43, no. 11, pp. 935-946, Mar. 2008.