Umit Ogras

Ogras_Umit_3750bAssistant Professor
ASU Directory Profile

Lab Website

Office: GWC 320
Phone: 480-727-0294
Fax: 480-965-0616
Email: umit@asu.edu

Research expertise
Digital VLSI design, embedded systems and electronic design automation with particular emphasis on multiprocessor systems-on-chip (MPSoC) and multicore architectures.

Umit Y. Ogras received his Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2007. From 2008 to 2013, he worked as a Research Scientist at the Strategic CAD Laboratories, Intel Corporation. He is currently an Assistant Professor at the School of Electrical, Computer and Energy Engineering. Recognitions Dr. Ogras has received include Strategic CAD Labs Research Award, 2012 IEEE Donald O. Pederson Transactions on CAD Best Paper Award, 2011 IEEE VLSI Transactions Best Paper Award and 2008 EDAA Outstanding PhD. Dissertation Award.  His research interests include digital system design, embedded systems, multicore architecture and electronic design automation with particular emphasis on multiprocessor systems-on-chip (MPSoC).

Professional preparation
Ph.D., Electrical and Computer Engineering, Carnegie Mellon University, 2007
M.S., Electrical Engineering, Ohio State University, 2002
B.S., Electrical Engineering, Middle East Technical University, Turkey, 2000

Recognition and awards
Strategic CAD Labs Research Award, 2012
IEEE Council on Electronic Design Automation 2012 Donald O. Pederson Trans. On CAD Best Paper Award, 2012
IEEE Circuits and Systems Society VLSI Transactions Best Paper Award, 2011
Intel Microprocessor Development Group Division Recognition Award, 2010
Outstanding PhD. Dissertation Award, 2008
Outstanding Teaching Assistant Award, CMU, 2007

Selected publications
Umit Ogras and Radu Marculescu. Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures. Lecture Notes in Electrical Engineering, Vol. 184, Springer, 2013.

R. Z. Ayoub, U. Y. Ogras, E. Gorbatov, Y. Jin, T. Kam, P. Diefenbaugh, T. Rosing, “OS-level Power Minimization under Tight Performance Constraints in General Purpose Systems,” in Proc. of Intl. Symp. on Low-power Electronics and Design, August 2011.

U. Y. Ogras, P. Bogdan, R. Marculescu, “An Analytical Approach for Network-on-Chip Performance Analysis,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, pp. 2001-2013, Dec. 2010.

U. Y. Ogras, R. Marculescu, D. Marculescu, E. G. Jung, “Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Special Section on Networks-on-Chip, vol. 17, pp. 330-341, March 2009.

R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, Y. Hoskote, “Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 28, pp. 3-21, Jan. 2009.