Yu Cao

Cao_Yu_KevinWEBAssociate Professor
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GWC 336

Research expertise
Physical modeling of nanoscale technologies, design solutions for variability and reliability, and reliable integration of post-silicon technologies

Kevin Cao joined the ASU faculty in 2004. He received a P.h.D in electrical engineering in 2002 and an M.A. in biophysics in 1999 from the University of California, Berkeley, and conducted his post-doctoral research at the Berkeley Wireless Research Center. He has published more than 150 articles and has co-authored one book on nano-CMOS physical and circuit design. He has served on the technical program committee of many conferences and is a member of the IEEE EDS Compact Modeling Technical Committee.

Collaborations and industry affiliations
Cao,Yu * . TERI: Techniques for Estimating Reliability without design modification of ICs. UNIV OF SOUTHERN CA (7/21/2011 – 1/20/2013).
Cao,Yu * . SHF:: Small: Collaborative Research: Fast Sign-Off of Nanoscale Memory: From Predictive Device Modeling to Statistical Circuit Synthesis. NSF-CISE-CCF (8/15/2010 – 7/31/2013).
Cao,Yu * . Scalable Technology Models for Alternative Devices and Interconnect. GEORGIA INST OF TECHNOLOGY (11/1/2009 – 10/31/2010).
Bakkaloglu,Bertan * Cao,Yu . EAGER: Low-Power VLSI Applications of Neuromorphic Circuit Construction with Nanoelectronic Devices. NSF-ENG-ECS (9/1/2009 – 8/31/2011).
Cao,Yu * . Benchmarking Nanoscale Circuit Design with Predictive Technology Model. QualComm (4/1/2008 – 12/31/2009).
Yu,Hongbin * Bakkaloglu,Bertan Cao,Yu Yan,Hao . Self-Assembled Inductors: A New Paradigm in Nanoelectronics Design. NSF-CISE (9/1/2007 – 8/31/2011).
Cao,Yu * . Predictive Modeling and Simulation of reliability Degradation in Nanoscale Circuits. SEMICONDUCTOR RESEARCH CORP (7/1/2007 – 6/30/2010).
Cao,Yu * . Benchmarking Nanoscale Circuit Design with Predictive Technology Model. QualComm (6/8/2007 – 9/30/2008).
Cao,Yu * . System Performance Prediction for Reliable Nanoscale Integration. UNIV OF CA AT BERKELEY (9/1/2006 – 10/31/2009).
Cao,Yu * . CAREER: Bridging the Technology-EDA Gap through Strategic Tools for Robust Nanometer Integration. NSF-CISE (8/15/2006 – 7/31/2011).
Cao,Yu * . Benchmakring Nanoscale Circuit Reliability with Predictive Technology Models. SEMICONDUCTOR RESEARCH CORP (9/1/2005 – 12/31/2006).
Cao,Yu * . Predictive Technology Modeling for Robust Nanometer Design. CARNEGIE MELLON UNIV (5/1/2005 – 10/31/2009).
Cao,Yu * . MIT MSD: Predictive Technology Modeling for Robust Nanometer Design. MASSACHUSETTS INST OF TECHNOLO (5/1/2005 – 10/31/2009).
Clark,LawrenceT * Cao,Yu . Robust Low Power Circuit Design with Predictive Technology Models. SEMICONDUCTOR RESEARCH CORP (1/1/2005 – 1/31/2006).

Professional preparation
Ph.D., electrical engineering, University of California, Berkeley, 2002
M.A., biophysics, University of California, Berkeley

Recognition and awards
Teaching Excellence Award, Ira. A. Fulton Schools of Engineering, ASU, 2010
Promotion and Tenure Faculty Exemplar, Arizona State University, 2009
Distinguished Lecturer of the IEEE Circuits and Systems Society, 2009
Chunhui Award for Outstanding Oversea Chinese Scholars, China, 2008
Best Paper Award at the International Low-Power Electronics and Design, 2007
IBM Faculty Award, 2007 and 2006
NSF Faculty Early Career Development (CAREER) Award, 2006
Best Paper Award at the International Symposium on Quality Electronic Design, 2004
Beatrice Winner Award, International Solid-State Circuits Conference, 2000
Biophysics Graduate Program Fellowship at the University of California, Berkeley, 1997-98
UC Regents Fellowship at University of California, Santa Cruz, 1996-97

Selected Publications
Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011.

W. Xu, S. Sinha, H. Wu, T. Dastagir, Y. Cao and H. Yu, “On-chip spiral inductors with integrated magnetic materials,” Chapter 17, pp. 439-462,  Advanced Circuits for Emerging Technologies, Edited by Kris Iniewski, John Wiley & Sons, Inc., 2012.

W. Wang, V. Reddy, S. Krishnan, Y. Cao, “Compact modeling for NBTI and CHC effects,” pp. 40-60, Recent Advancements in Modeling of Semiconductor Processes, Circuits and Chip-Level Interactions, Edited by Rasit Onur Topaloglu and Peng Li, Bentham Science Publishers Ltd., 2011

W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao, “The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis,” IEEE Transactions on VLSI Systems, vol. 18, no. 2, pp. 173-183, 2010.

T. Austin, V. Bertacco, Y. Cao, and S. Mahlke, “Reliable systems on unreliable fabrics,” IEEE Design & Test of Computers, vol. 25, no. 4, pp. 322-332, July-Aug., 2008.

B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” Proceedings of the IEEE, vol. 96, no. 2, pp. 343-365, Feb. 2008.