Jae-sun Seo

Assistant Professor
ASU Directory Profile
Personal Webpage

jaesun.seo@asu.edu

ISTB4 551B

Research interests: Digital/mixed-signal circuit design, VLSI design for neuromorphic computing and machine learning, integrated voltage regulators, high-speed on-chip transceivers

Jae-sun Seo joined ASU in 2014. He received a bachelor’s degree from Seoul National University in 2001, and a master’s degree and Ph.D. from the University of Michigan in 2006 and 2010, respectively, all in electrical engineering. From January 2010 to December 2013, he was with IBM T. J. Watson Research Center, where he worked on energy-efficient integrated circuits for high-performance processors and cognitive computing chips.

During the summer of 2015, he was a visiting faculty at Intel Circuits Research Lab. His current areas of research include machine learning and neuromorphic hardware design, and on-chip voltage regulators for integrated power management. He serves on the technical program committee for ISLPED and ISOCC, and the organizing committee for ICCD.

Professional preparation
Ph.D., electrical engineering, University of Michigan, 2010
M.S., electrical engineering, University of Michigan, 2006
B.S., electrical engineering, Seoul National University, 2001

Recognition and awards
IBM Major Outstanding Technical Achievement Award, 2012
IBM Invention Achievement Award, 2011
Samsung Scholarship Foundation Fellow, 2004-2009

Selected publications

S. Bang, J. Seo, L. Chang, D. Blaauw, and D. Sylvester, “A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering,” IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 919-929, April 2016.

J. Seo, B. Lin, M. Kim, P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, S. Vrudhula, S. Yu, J. Ye, Y. Cao, “On-Chip Sparse Learning Acceleration with CMOS and Resistive Synaptic Devices,” IEEE Transactions on Nanotechnology (TNANO), vol. 14, no. 6, pp. 969-979, November 2015.

B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishnan, L. Chang, D. Friedman, and M. Ritter, “Specifications of Nanoscale Devices & Circuits for Neuromorphic Computational Systems,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 246-253, January 2013.

J. Seo, D. Blaauw, and D. Sylvester, “Crosstalk-Aware PWM-Based On-Chip Links with Self-Calibration in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), September 2011, vol. 46, no. 9, pp. 2041-2052, September 2011.

J. Seo, B. Brezzo, Y. Liu, B. Parker, S. Esser, R. Montoye, B. Rajendran, J. Tierno, L. Chang, D. Modha, and D. Friedman, “A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons,” IEEE Custom Integrated Circuit Conference (CICC), September 2011.

J. Seo, R. Ho, J. Lexau, M. Dayringer, D. Sylvester, and D. Blaauw, “High-Bandwidth and Low-Energy On-Chip Signaling with Adaptive Pre-Emphasis in 90nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 182-183, February 2010.