ASU Directory Profile
Research expertise: Circuits and architectures for low power and high performance VLSI for harsh environments, CAD for VLSI
Lawrence T. Clark worked at Intel Corporation after receiving his bachelor’s degree in computer science in 1983. While completing doctoral studies he worked at VLSI Technology Inc. designing PC chipsets. He received his Ph.D. in 1992 after receiving his M.S. in 1987, both in electrical engineering from Arizona State University. He re-joined Intel in 1992. Clark joined ASU in August 2004. Professor Clark has been awarded over 115 patents with approximately 10 pending. He has published more than 130 peer-reviewed technical papers and nine book chapter. He has about 20 years of industry experience in various aspects of VLSI, CMOS imager, microprocessor design, test engineering, as well as TCAD compact modeling. At Intel he contributed to the Pentium, Itanium and XScale microprocessor designs. Most recently, he was a principal engineer and circuit design manager for the Intel XScale microprocessor designs. He also worked with SuVolta Inc. from 2009-2014, where he was chief architect.
Collaborations and industry affiliations
Allee,DavidRay * , Clark,LawrenceT , . Neutron Detector. UNIV OF TEXAS-DALLAS (6/7/2010 – 12/31/2012).
Clark,LawrenceT * . Development of the Highly Efficient Rad-hard-by-design Microprocessor for Enabling Spacecraft (HERMES). JPL (3/10/2010 – 2/27/2011).
Vermeire,Bert * Clark,LawrenceT . Design of a hardened SDRAM integrated Circuit. SPACE MICRO, INC (7/1/2009 – 6/30/2010).
Clark,LawrenceT * Allee,DavidRay . Support Micro-RDC on the Advanced IC Design Techniques for the Prevention of Reverse Engineering of the Programmed Functionality in FPGAs. Micro-RDC (1/7/2008 – 9/14/2009).
Clark,LawrenceT * Barnaby,HughJames Holbert,KeithEdwin . High Performance, Low Power Radiation Hardened by Design Microprocessor Techniques. DOD-AFRL (8/14/2007 – 12/28/2012).
Clark,LawrenceT * . Ultra-Fast Level 2 Cache SRAM for High-Performance Military and Spaceborne Computing. Micro-RDC (3/5/2007 – 8/27/2007).
Ph.D., electrical engineering, Arizona State University, 1992
M.S., electrical engineering, Arizona State University, 1987
B.S., computer science, Northern Arizona University, 1984
Recognition and awards
Senior member, IEEE
Recipient of the Intel Achievement Award and multiple Intel divisional recognition awards
Best Paper Award, Int. Symposium on Low Power Design (ISLPED) 2013
Technical committee member for IEEE Custom Integrated Circuits Conference
Previous committee member for IEEE Nuclear and Space Radiation Effects Conference (NSREC) and Int. Symposium on Low Power Design (ISLPED)
Previous associate editor, IEEE Transactions on Circuits and Systems II
Previous guest editor, IEEE Journal of Solid State Circuits and IEEE Transactions on Circuits and Systems I.
Senior member of IEEE
L. T. Clark, S. Leshner and G. Tien, “SRAM Cell Optimization for Low AVT Transistors,” Proc. ISLPED, 2013. Winner of Best Paper Award.
L. T. Clark, D. Patterson, C. Ramamurthy, and K. Holbert, “A Microprocessor Core Hardened by Microarchitecture and Circuit Techniques,” IEEE Trans. Computers.,” 2015.
S. Chellappa and L. T. Clark, “SRAM Based Unique Chip Identifier Techniques,” IEEE Trans. VLSI Sys.,” 2015.
S. Shambhulingaiah, C. Lieb, and L. T. Clark, “Circuit Simulation Based Validation of Flip-flop Robustness to Multiple Node Charge Collection,” IEEE Trans. Nucl. Sci.,” 2015.
L. T. Clark, L. Shifren, V. Vashishthaa, A. Gujja, S. Sinha, B. Cline, C. Ramamurthya, and G. Yeric, “ASAP7: A 7-nm FinFET Predictive Process Design Kit,” Microelectronics Journal, vol. 53, pp. 105-115, July 2016.
C. Farnsworth, V. Vashishtha, L. T. Clark, S. Chellappa, A. Gogulamudi, and A. Gujja, , “A Soft-Error Hardened Process Portable Embedded Microprocessor,” IEEE Trans. Nucl. Sci., 2016.