ASU Faculty Since: 2013
Research expertise: Emerging nano-devices and circuits beyond CMOS technology, new computing paradigms beyond von-Neumann architecture
Shimeng Yu received a bachelor’s degree in microelectronics from Peking University in 2009, and a master’s degree and Ph.D. in electrical engineering from Stanford University in 2011 and in 2013, respectively. He did summer internships in IMEC, Belgium in 2011, and IBM TJ Watson Research Center in 2012. He is currently an assistant professor of electrical engineering and computer engineering at Arizona State University.
His research interests are emerging nano-devices and circuits beyond CMOS technology with focus on the resistive switching memories, and new computing paradigms beyond von-Neumann architecture with a focus on the brain-inspired neuromorphic computing. He has published more than 30 journal papers and 70 conference papers with over 2,000 citations and an H-index of 24.
He has served on the Technical Committee of Nanoelectronics and Gigascale Systems, IEEE Circuits and Systems Society since 2014.
Ph.D., electrical engineering, Stanford University, 2013
M.S., electrical engineering, Stanford University, 2011
B.S., microelectronics, Peking University, 2009
Recognition and awards
Stanford Graduate Fellowship, 2009-2012
IEEE Electron Devices Society Masters Student Fellowship, 2010
IEEE Electron Devices Society PhD Student Fellowship, 2012
Yu, P.-Y. Chen, Y. Cao, L. Xia, Y. Wang, H. Wu, “Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect,” IEEE International Electron Devices Meeting (IEDM) 2015, Washington DC, USA, invited.
P.-Y. Chen, B. Lin, I.-T. Wang, T.-H. Hou, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, and S. Yu, “Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2015, Austin, TX, USA.
P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, S. Yu, “Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,” IEEE Design, Automation & Test in Europe (DATE) 2015, Grenoble, France.
P.-Y. Chen, R. Fang, R. Liu, C. Chakrabarti, Y. Cao, S. Yu, “Exploiting resistive cross-point array for compact design of physical unclonable function,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 2015, Washington DC, USA.
Fang, Y. Gonzalez-Velo, W. Chen, K. Holbert, M. Kozicki, H. Barnaby, S. Yu, “Total ionizing dose effect of γ-ray radiation on the switching characteristics and filament stability of HfOx resistive random access memory,” Appl. Phys. Lett., 104, 183507, 2014.
Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A low energy oxide-based electronic synaptic device for neuromorphic visual system with tolerance to device variation,” Adv. Mater., vol. 25, no. 12, pp. 1774-1779, 2013.
Yu, H.-Y. Chen, B. Gao, J. F. Kang, and H.-S. P. Wong, “A HfOx based vertical resistive switching random access memory for bit-cost-effective three-dimensional cross-point architecture,” ACS Nano, vol. 7, no. 3, pp. 2320-2325, 2013.
Yu, H.-Y. Chen, Y. Deng, B. Gao, Z. Jiang, J. F. Kang, and H.-S. P. Wong, “3D vertical RRAM – scaling limit analysis and demonstration of 3D array operation,” Symposium on VLSI Technology (VLSI)2013, pp. 158-159, Kyoto, Japan.
Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Understanding the conduction and switching mechanism of metal oxide RRAM through low frequency noise and AC conductance measurement and analysis,” IEEE International Electron Devices Meeting (IEDM) 2011, pp. 275-278, Washington DC, USA.
Yu, X. Guan, and H.-S. P. Wong, “On the stochastic nature of resistive switching in metal oxide RRAM: physical modeling, Monte Carlo simulation, and experimental characterization,” IEEE International Electron Devices Meeting (IEDM) 2011, pp. 413-416, Washington DC, USA.