Shimeng Yu

Assistant Professor
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ISTB4 555C
(480) 727-1900
Shimeng.Yu@asu.edu

ASU Faculty Since: 2013

Research expertise: Emerging nano-devices and circuits beyond CMOS technology, new computing paradigms beyond von-Neumann architecture

Shimeng Yu received a bachelor’s degree in microelectronics from Peking University in 2009, and a master’s degree and Ph.D. in electrical engineering from Stanford University in 2011 and in 2013, respectively. He is currently an assistant professor of electrical engineering and computer engineering at Arizona State University.

His research interests are emerging nano-devices and circuits beyond CMOS technology with focus on the resistive switching memories, and new computing paradigms beyond von-Neumann architecture with a focus on the brain-inspired neuromorphic computing. He has published more than 50 journal papers and more than 90 conference papers with over 3,000 citations and an H-index of 26.

He did summer internship in IMEC, Belgium in 2011, and IBM TJ Watson Research Center in 2012. He held visiting faculty position in Tsinghua University in 2016, and Air Force Research Laboratory in 2016. He has been serving the Technical Committee of Nanoelectronics and Gigascale Systems, IEEE Circuits and Systems Society since 2014.

Professional preparation
Ph.D., electrical engineering, Stanford University, 2013
M.S., electrical engineering, Stanford University, 2011
B.S., microelectronics, Peking University, 2009

Recognition and awards
Stanford Graduate Fellowship, 2009-2012
IEEE Electron Devices Society Masters Student Fellowship, 2010
IEEE Electron Devices Society PhD Student Fellowship, 2012
DOD-DTRA Young Investigator Award, 2015
NSF CAREER Award, 2016

Selected publications

S. Yu, Resistive Random Access Memory (RRAM): From Devices to Array Architectures, Synthesis Lectures on Emerging Engineering Technologies 2 (5), 1-79, Publisher: Morgan & Claypool, 2016.

S. Yu, P.-Y. Chen, “Emerging memory technologies: recent trends and prospects,” IEEE Solid State Circuits Magazine, vol. 8, no. 2, pp. 43-56, 2016, invited review.

L. Gao, P.-Y. Chen, S. Yu, “Demonstration of convolution kernel operation on resistive cross-point array,” IEEE Electron Device Letters, vol. 37, no. 7, 870-873, 2016.

R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “Experimental characterization of physical unclonable function based on 1kb resistive random access memory arrays,” IEEE Electron Device Letters, vol. 36, no. 12, pp. 1380-1383, 2015.

S. Yu, P.-Y. Chen, Y. Cao, L. Xia, Y. Wang, H. Wu, “Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect,” IEEE International Electron Devices Meeting (IEDM) 2015, Washington DC, USA, invited.

P.-Y. Chen, B. Lin, I.-T. Wang, T.-H. Hou, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, and S. Yu, “Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2015, Austin, TX, USA.

P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, S. Yu, “Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,” IEEE Design, Automation & Test in Europe (DATE) 2015, Grenoble, France.

S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A low energy oxide-based electronic synaptic device for neuromorphic visual system with tolerance to device variation,” Advanced Materials., vol. 25, no. 12, pp. 1774-1779, 2013.

S. Yu, H.-Y. Chen, B. Gao, J. F. Kang, and H.-S. P. Wong, “A HfOx based vertical resistive switching random access memory for bit-cost-effective three-dimensional cross-point architecture,” ACS Nano, vol. 7, no. 3, pp. 2320-2325, 2013.

S. Yu, H.-Y. Chen, Y. Deng, B. Gao, Z. Jiang, J. F. Kang, and H.-S. P. Wong, “3D vertical RRAM – scaling limit analysis and demonstration of 3D array operation,” Symposium on VLSI Technology (VLSI)2013, pp. 158-159, Kyoto, Japan.