Umit Ogras

Assistant Professor
ASU Directory Profile

Lab Website

Office: ISTB4 551A
Phone: 480-727-0294
Fax: 480-965-0616

Research interests: Digital VLSI design, embedded systems, multiprocessor systems-on-chip (MPSoC), multicore architectures, electronic design automation

Umit Y. Ogras joined ASU as an assistant professor in 2013. Ogras received his Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 2007. From 2008 to 2013, he worked as a research scientist at the Strategic CAD Laboratories, Intel Corporation. His research interests are in low-power VLSI systems and embedded system design. In particular, his research focuses on design methodologies and power management for multicore architectures.

Professional preparation
Ph.D., Electrical and Computer Engineering, Carnegie Mellon University, 2007
M.S., Electrical Engineering, Ohio State University, 2002
B.S., Electrical Engineering, Middle East Technical University, Turkey, 2000

Recognition and awards
Strategic CAD Labs Research Award, 2012
IEEE Council on Electronic Design Automation, 2012
Donald O. Pederson Trans. On CAD Best Paper Award, 2012
IEEE Circuits and Systems Society VLSI Transactions Best Paper Award, 2011
Intel Microprocessor Development Group Division Recognition Award, 2010
Outstanding PhD. Dissertation Award, 2008
Outstanding Teaching Assistant Award, CMU, 2007

Selected publications

Md Muztoba, Ujjwal Gupta, Tanvir Mustofa, Umit Y. Ogras, “Robust Communication with IoT Devices using Wearable Brain Machine Interfaces,” in Proc. of Intl. Conference on Computer-Aided Design, November 2015.

Ujjwal Gupta, Sankalp Jain, Umit Y. Ogras, “Can Systems Extended to Polymer? SoP Architecture Design and Challenges,” in Proc. of the Intl. SoC (System-on-Chip) Conference, September 2015.

Ujjwal Gupta, Spurthi Korrapati, Navyasree Matturu, and Umit Y. Ogras, “A Generic Energy Optimization Framework for Heterogeneous Platforms using Scaling Models,” in Elsevier Microprocessors and Microsystems, June 2015.

Umit Ogras and Radu Marculescu. Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures. Lecture Notes in Electrical Engineering, Vol. 184, Springer, 2013.

Y. Ogras, P. Bogdan, R. Marculescu, “An Analytical Approach for Network-on-Chip Performance Analysis,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, pp. 2001-2013, Dec. 2010. (IEEE D.O. Pederson Trans. On CAD Best Paper Award)

Y. Ogras, R. Marculescu, D. Marculescu, E. G. Jung, “Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Special Section on Networks-on-Chip, vol. 17, pp. 330-341, March 2009. (IEEE T-VLSI Best Paper Award)