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Engineering | School of Electrical, Computer and Energy Engineering

Designing the computational architecture of the future

Designing the computational architecture of the future

As advances in 21st-century engineering and science increase in number and rapidity, the progress only arouses stronger ambitions to achieve even bigger discoveries and broader technological capabilities.

Many of those aspirations are constrained by the limitations of current computing technologies, says Daniel Bliss, an associate professor of electrical, computer and energy engineering in Arizona State University’s Ira A. Fulton Schools of Engineering.

“I am always computation hungry. I’m interested in taking steps forward on a lot of advanced communications, radar and medical systems, but I never have the computational ability I need,” says Bliss, a systems engineer.

That’s why he is eager to begin work on what for him is a dream endeavor. Bliss is leading one of many research efforts being pursued under the new national Electronics Resurgence Initiative headed by the U.S. Defense Advanced Research Projects Agency, commonly known as DARPA, an agency of the Department of Defense.

Under the direction of DARPA’s Microsystems Technology Office, the initiative’s mission is to spark innovative solutions to overcome obstacles that have impeded significant evolution in microelectronic systems — including computing systems.

More specifically, the goals of the DARPA initiative’s Domain-Specific System on Chip (DSSoC) program align precisely with the aims of ASU’s Center for Wireless Information Systems and Computational Architectures, which Bliss directs.

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Posted on

July 25, 2018