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Engineering | School of Electrical, Computer and Energy Engineering

Yu (Kevin) Cao

ASU Directory Profile

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ISTB4 563

Research expertise: Physical modeling of nanoscale technologies, design solutions for variability and reliability, and neural-inspired hardware and algorithms for learning

Kevin Cao joined the ASU faculty in 2004. He received a doctoral degree in electrical engineering in 2002 and a master’s degree in biophysics in 1999 from the University of California, Berkeley, and conducted his post-doctoral research at the Berkeley Wireless Research Center. He has published more than 200 articles, two books, eight book chapters, and five patents. He has served on the technical program committee of many conferences and is an Associated Editor of the IEEE Transactions on CAD.

Collaborations and industry affiliations
Cao,Yu * . TERI: Techniques for Estimating Reliability without design modification of ICs. UNIV OF SOUTHERN CA (7/21/2011 – 1/20/2013).
Cao,Yu * . SHF:: Small: Collaborative Research: Fast Sign-Off of Nanoscale Memory: From Predictive Device Modeling to Statistical Circuit Synthesis. NSF-CISE-CCF (8/15/2010 – 7/31/2013).
Cao,Yu * . Scalable Technology Models for Alternative Devices and Interconnect. GEORGIA INST OF TECHNOLOGY (11/1/2009 – 10/31/2010).
Bakkaloglu,Bertan * Cao,Yu . EAGER: Low-Power VLSI Applications of Neuromorphic Circuit Construction with Nanoelectronic Devices. NSF-ENG-ECS (9/1/2009 – 8/31/2011).
Cao,Yu * . Benchmarking Nanoscale Circuit Design with Predictive Technology Model. QualComm (4/1/2008 – 12/31/2009).
Yu,Hongbin * Bakkaloglu,Bertan Cao,Yu Yan,Hao . Self-Assembled Inductors: A New Paradigm in Nanoelectronics Design. NSF-CISE (9/1/2007 – 8/31/2011).
Cao,Yu * . Predictive Modeling and Simulation of reliability Degradation in Nanoscale Circuits. SEMICONDUCTOR RESEARCH CORP (7/1/2007 – 6/30/2010).
Cao,Yu * . Benchmarking Nanoscale Circuit Design with Predictive Technology Model. QualComm (6/8/2007 – 9/30/2008).
Cao,Yu * . System Performance Prediction for Reliable Nanoscale Integration. UNIV OF CA AT BERKELEY (9/1/2006 – 10/31/2009).
Cao,Yu * . CAREER: Bridging the Technology-EDA Gap through Strategic Tools for Robust Nanometer Integration. NSF-CISE (8/15/2006 – 7/31/2011).
Cao,Yu * . Benchmakring Nanoscale Circuit Reliability with Predictive Technology Models. SEMICONDUCTOR RESEARCH CORP (9/1/2005 – 12/31/2006).
Cao,Yu * . Predictive Technology Modeling for Robust Nanometer Design. CARNEGIE MELLON UNIV (5/1/2005 – 10/31/2009).
Cao,Yu * . MIT MSD: Predictive Technology Modeling for Robust Nanometer Design. MASSACHUSETTS INST OF TECHNOLO (5/1/2005 – 10/31/2009).
Clark,LawrenceT * Cao,Yu . Robust Low Power Circuit Design with Predictive Technology Models. SEMICONDUCTOR RESEARCH CORP (1/1/2005 – 1/31/2006).

Professional preparation
Ph.D., electrical engineering, University of California, Berkeley, 2002
M.A., biophysics, University of California, Berkeley

Recognition and awards
Best paper award, IEEE Computer Society Annual Symposium on VLSI (2012)
Teaching Excellence Award, Ira. A. Fulton Schools of Engineering, ASU, 2010
Promotion and Tenure Faculty Exemplar, Arizona State University, 2009
Distinguished Lecturer of the IEEE Circuits and Systems Society, 2009
Chunhui Award for Outstanding Oversea Chinese Scholars, China, 2008
Best Paper Award at the International Low-Power Electronics and Design, 2007
IBM Faculty Award, 2007 and 2006
NSF Faculty Early Career Development (CAREER) Award, 2006
Best Paper Award at the International Symposium on Quality Electronic Design, 2004
Beatrice Winner Award, International Solid-State Circuits Conference, 2000
Biophysics Graduate Program Fellowship at the University of California, Berkeley, 1997-98
UC Regents Fellowship at University of California, Santa Cruz, 1996-97

Selected Publications
Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011.

K. B. Sutaria, A. Mohanty, R. Wang, R. Huang, Y. Cao, “Accelerated aging in analog and digital circuits with feedback,” to be published in IEEE Transactions on Device and Materials Reliability.

D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J. Seo, “Parallel architecture with resistive crosspoint array for dictionary learning acceleration,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on Solid-State Memristive Devices and Systems, vol. 5, no. 2, pp. 194-204, 2015.

Y. Cao, J. Velamala, K. Sutaria, M. S.-W. Chen, J. Ahlbin, I. S. Esqueda, M. Bajura, M. Fritze, “Cross-layer modeling and simulation of circuit reliability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 8-23, January 2014.

J. B. Velamala, K. B. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Y. Cao, “Compact modeling of statistical BTI under trapping/detrapping,” IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3645-3654, November 2013.

J. Suh, N. Suda, C. Xu, N. Hakim, Y. Cao, B. Bakkaloglu, “Programmable analog device array (PANDA): a methodology for transistor-level analog emulation,” IEEE Transactions on Circuits and Systems I, vol. 60, no. 6, pp. 1369-1380, June 2013.